1. Field of the Invention:
This invention relates to a switch data input device for reading the on-off states of switches and, more particularly, to such a device which is used in cameras.
2. Description of the Related Art:
The camera or like instrument has its electrical circuitry made operational with the electrical power source restricted in availability to what is called battery. The microcomputer introduced into such a system has, therefore, generally a program that enables the consumption of electrical energy from the battery to be saved as much as possible. To this end, the microcomputer usually waits for an interrupt signal. During this waiting time (or in the so-called "HALT" state), the consumed current is limited to as little as 10 microamperes or thereabout. In response to an external event that whichever of the switches changes from the open (off) state to the closed (on) state, or an interrupt signal, the program of the microcomputer is initiated to run so that the state of the switch is read in, and a corresponding data handling routine to the read data is executed.
And, to this purpose, the conventional device was so constructed that so long as the switch was left unchanged from the "on" state to the "off" state, the interrupt signal substantially continued being produced. In other words, the interrupt capability was not more than that, under the condition that the first switch is in the "on" state, even if another or second switch is turned on, no more interrupt signal representing the new event is produced. By the given interrupt signal, therefore, it was impossible to discriminate between the successive events.
To compensate for this, according to the prior art, the switch data input device was provided with a program that if any successive two cycles of reading the state of the first switch have the same result, transferring to the HALT state is effected. If not the same result, then, as it implies that another switch has been turned on, a special routine dealing with the new event is executed.
The conventional device of such structure, because of the necessity of carrying out all but one cycle of reading operation of the first switch in vain until another switch changes its state, had a drawback that too much electrical power was consumed wastefully.
Also, the program for the microcomputer must include the special routine in which, as has been described above, the switch data (also called "key input") of the preceding cycle is put in the memory or RAM, then a newly read key input is compared with it, and then the comparison result is tested. The software to be used became redundant and the programming work became troublesome and time consuming.
The foregoing example of the conventional device is described in greater detail below.
In FIG. 9, the microcomputer .mu.COM enclosed within a dashed line block has eight key input terminals IN0-IN7 to which are connected respective switches SW0-SW7 at their throws, of which the movable poles are grounded (connected to circuit earth). In the example of FIG. 9, therefore, when any of the switches (SW0-SW7) turns on (is closed), the potential at the corresponding input terminal changes to a low level. Pull-up registers R0-R7 for the terminals IN0-IN7 maintain the respective input data at logic-1 (assuming a high level) when the switches are open. CPU represents the core of the microcomputer or is a so-called central processing unit including a ROM (read-only memory), RAM (random-access memory) and ALU (arithmetic and logical unit) as is well known in the art. When at least one of the switches SW0-SW7 turns on, a D-type flip-flop DFFR produces an interrupt signal INTR. Responsive to this signal, the CPU executes the corresponding task for the data from the switches SW0-SW7 through read buffers BUF0-FUP7 in the form of tri-state buffers. The inputs of the buffers BUF0-BUF7 are connected to the input terminals IN0-IN7 and their outputs are connected to data bus lines D0-D7 respectively. The enable-to-output terminals of the buffers BUF0-BUF7 all are connected to a common line at which a read enable signal RDEN from the CPU appears. When read out information concerning the binary logic at the input terminals IN0-IN7, the CPU changes the signal RDEN to a high level, thereby the outputs of the buffers BUF0-BUF7 are transferred thereto through the data bus lines D0-D7.
NAND is an 8-input NAND gate (in the instance of FIG. 9, described by negative logic) responsive to a low level at any one of its eight inputs for producing an output at a high level. When the output of the NAND gate NAND changes from a low to high level, the D-type flip-flop DFFR, because of its D-terminal being set always at a high level, changes and maintains its Q output to a high level until the potential at its "reset" input R later reaches a high level.
With the switch data input device of such construction, when any one of the switches SW0-SW7 turns on, the corresponding one of the input terminals IN0-IN7 reaches a low level, causing the output of the NAND gate NAND to change from a low to a high level. Therefore, the output Q of the D-type flip-flop DFFR reaches a high level. Thus, the interrupt signal INTR that requests the CPU to interrupt a running program in response to the key input. As the CPU recognizes this signal INTR, when the execution of the interrupt routine is initiated, its output signal INTCLR is changed to a high level to reset the D-type flip-flop DFFR. Hence, the signal INTR is removed to render the CPU responsive to the next interrupting event. Now assuming that any of the switches SW0-SW7 is left in the "on" state, then the output of the NAND gate NAND retains a high level. Therefore, even if another switch turns on later, a new interrupt signal never generates as has been described above. So, it has been the practice in the prior art to test if another switch has been turned on in such a way that after the completion of execution of a step #5 of FIG. 10 for the corresponding task (data handling) to the first key input, a vain interrupting operation shown in steps #6-#8 is always carried out.
Therefore, the conventional device had drawbacks that the consumption of electrical power was increased by always performing vain reading operation and the program became redundant.
The circuit of FIG. 9 further includes an electrical power source or battery BAT of which the power supply line is connected to the microcomputer .mu.COM, a PNP transistor TR, a resistor R.sub.BE and another integrated circuit IC which is controlled by the microcomputer .mu.COM through control and data buses BUS. When the microcomputer .mu.COM changes its output signal V.sub.ON to a low level, the transistor TR is turned on to supply current from the battery BAT to the integrated circuit IC therethrough.